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cy15b004q 4-kbit (512 8) serial (spi) automotive f-ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-10032 rev. *c revised april 5, 2017 4-kbit (512 8) serial (spi) automotive f-ram features 4-kbit ferroelectric random access memory (f-ram) logically organized as 512 8 ? high-endurance 10 trillion (10 13 ) read/writes ? 121-year data retention (see the data retention and endurance table) ? nodelay? writes ? advanced high-reliability ferroelectric process very fast serial peripheral interface (spi) ? up to 16 mhz frequency ? direct hardware replacement for serial flash and eeprom ? supports spi mode 0 (0, 0) and mode 3 (1, 1) sophisticated write protection scheme ? hardware protection using the write protect (wp ) pin ? software protection using write disable instruction ? software block protection for 1/4, 1/2, or entire array low power consumption ? 200 a active current at 1 mhz ? 6 a (typ) standby current at +85 c low-voltage operation: v dd = 3.0 v to 3.6 v automotive-e temperature: ?40 c to +125 c 8-pin small outline integrated circuit (soic) package aec q100 grade 1 compliant restriction of hazardous substances (rohs) compliant functional description the cy15b004q is a 4-kbit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or f-ram is nonvolatile and performs reads and writes similar to a ram. it provides reliable data retention for 121 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash, eeprom, and other nonvolatile memories. unlike serial flash and eeprom, the cy15b004q performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte is successfully transferred to the device. the next bus cycle can commence without the need for data polling. in addition, the product offers substantial write endurance compared with other nonvolatile memories. the cy15b004q is capable of supporting 10 13 read/write cycles, or 10 millio n times more write cycles than eeprom. these capabilities make the cy15b004q ideal for nonvolatile memory applications requirin g frequent or rapid writes. examples range from data collecti on, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or eeprom can cause data loss. the cy15b004q provides substantial benefits to users of serial eeprom or flash as a hardwa re drop-in replacement. the cy15b004q uses the high-speed spi bus, which enhances the high-speed write capability of f-ram technology. the device specifications are guaranteed ov er an automotive-e temperature range of ?40 c to +125 c. instruction decoder clock generator control logic write protect instruction register address register counter 512 x 8 f-ram array 9 data i/ o register 8 nonvolatile status register 2 wp cs hold sck so si logic block diagram errata: the write enable latch (wel) bit in the status register of cy15b004q part doesn?t clear after executing the memory write (write ) operation at memory location(s) from 0x100 to 0x1ff. for more information, see errata on page 19 . details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability.
cy15b004q document number: 002-10032 rev. *c page 2 of 22 contents pinout ................................................................................ 3 pin definitions .................................................................. 3 functional overview ........................................................ 4 memory architecture ........................................................ 4 serial peripheral interface ? spi bus .............................. 4 spi overview ............................................................... 4 spi modes ................................................................... 5 power up to first access .... ........................................ 6 command structure .................................................... 6 wren - set write enable latch .......... .............. ......... 6 wrdi - reset write enable latch ............................... 6 status register and write prot ection ............................. 6 rdsr - read status register ..................................... 7 wrsr - write status register .................................... 7 memory operation ............................................................ 8 write operation ........................................................... 8 read operation ........................................................... 8 hold pin operation ................................................... 9 endurance ................................................................. 10 maximum ratings ........................................................... 11 operating range ............................................................. 11 dc electrical characteristics ........................................ 11 data retention and endurance ..................................... 12 example of an f-ram life time in an aec-q100 automotive application ..................... 12 capacitance .................................................................... 12 thermal resistance ........................................................ 12 ac test conditions ........................................................ 12 ac switching characteristics ....................................... 13 power cycle timing ....................................................... 15 ordering information ...................................................... 16 ordering code definitions ..... .................................... 16 package diagrams .......................................................... 17 acronyms ........................................................................ 18 document conventions ................................................. 18 units of measure ....................................................... 18 errata ............................................................................... 19 part numbers affected .............................................. 19 qualification status ................................................... 19 errata summary .................... .................................... 19 document history page ................................................. 21 sales, solutions, and legal information ...................... 22 worldwide sales and design s upport ......... .............. 22 products .................................................................... 22 psoc? solutions ...................................................... 22 cypress developer community ................................. 22 technical support ................. .................................... 22
cy15b004q document number: 002-10032 rev. *c page 3 of 22 pinout figure 1. 8-pin soic pinout hold sck 1 2 3 4 5 cs 8 7 6 v dd si so top view not to scale v ss wp pin deinitions pin name i/o type description cs input chip select . this active low input activates the device. when high, the device enters low-power standby mode, ignores other inputs, and tristate s the output. when low, the device internally activates the sck signal. a falling edge on cs must occur before every opcode. sck input serial clock . all i/o activity is synchronized to the seri al clock. inputs are latched on the rising edge and outputs occur on the falling edge. because the device is synchronous, the clock frequency may be any value between 0 and 16 mhz and may be interrupted at any time. si [1] input serial input . all data is input to the device on this pin. the pin is sampled on the rising edge of sck and is ignored at other times. it should alwa ys be driven to a valid logic level to meet i dd specifications. so [1] output serial output . this is the data output pin. it is driven dur ing a read and remains tristated at all other times including when hold is low. data transitions are driven on the falling edge of the serial clock. wp input write protect . this active low pin prevents all write o peration, including status register. if high, write access is determined by the other write prot ection features, as controlled through the status register. a complete explanation of write protection is provided in status register and write protection on page 7 . this pin must be tied to v dd if not used. hold input hold pin . the hold pin is used when the host cpu must in terrupt a memory operation for another task. when hold is low, the current oper ation is suspended. the device ignores any transition on sck or cs . all transitions on hold must occur while sck is low. this pin must be tied to v dd if not used. v ss power supply ground for the device. must be connected to the gr ound of the system. v dd power supply power supply input to the device. note 1. si may be connected to so for a single pin data interface .
cy15b004q document number: 002-10032 rev. *c page 4 of 22 functional overview the cy15b004q is a serial f-ram memory. the memory array is logically organized as 512 8 bits and is accessed using an industry standard serial peripheral interface (spi) bus. the functional operation of the f-ram is similar to serial flash and serial eeproms. the majo r difference between the cy15b004q and a serial flash or eeprom with the same pinout is the f-ram?s superior write performance, high endurance, and low power consumption. memory architecture when accessing the cy15b004q, the user addresses 512 locations of eight data bits each. these eight data bits are shifted in or out serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an opcode including the upper address bit, and a word address. the word address consist of the lower 8-address bits. the complete address of 9 bits specifies each byte address uniquely. most functions of the cy15b004q are either controlled by the spi interface or handled by on-board circuitry. the access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. th at is, the memory is read or written at the speed of the spi bus. unlike a serial flash or eeprom, it is not necessary to poll the device for a ready condition because writes occur at bus speed. by the time a new bus transaction can be shifted in to the device, a write operation is complete. this is explained in more detail in the interface section. note the cy15b004q contains no power management circuits other than a simple internal power-on reset circuit. it is the user?s responsibility to ensure that v dd is within datasheet tolerances to prevent incorrect operation. it is recommended that the part is not powered down with chip enable active. serial peripheral interface ? spi bus the cy15b004q is a spi slave device and operates at speeds up to 16 mhz. this high-speed serial bus provides high-performance serial communication to a spi master. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcon trollers that do not. the cy15b004q operates in spi mode 0 and 3. spi overview the spi is a four-pin inte rface with chip select (cs ), serial input (si), serial output (so), a nd serial clock (sck) pins. the spi is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. a device on the spi bus is activated using the cs pin. the relationship between chip select, clock, and data is dictated by the spi mode. this device supports spi modes 0 and 3. in both of these modes, data is clocked into the f-ram on the rising edge of sck starting from the first rising edge after cs goes active. the spi protocol is controlled by opcodes. these opcodes specify the commands from the bus master to the slave device. after cs is activated, the first byte transferred from the bus master is the opcode. followin g the opcode, any addresses and data are then transferred. the cs must go inactive after an operation is complete and before a new opcode can be issued. the commonly used terms in the spi protocol are as follows: spi master the spi master device controls the operations on a spi bus. an spi bus may have only one master with one or more slave devices. all the slaves share the same spi bus lines and the master may select any of t he slave devices using the cs pin. all of the operations must be initiated by the master activating a slave device by pulling the cs pin of the slave low. the master also generates the sck and all the data transmission on si and so lines are synchronize d with this clock. spi slave the spi slave device is activated by the master through the chip select line. a slave device gets th e sck as an input from the spi master and all the communicat ion is synchronized with this clock. an spi slave never in itiates a communication on the spi bus and acts only on the instruction from the master. the cy15b004q operates as an spi slave and may share the spi bus with other spi slave devices. chip select (cs ) to select any slave device, the master needs to pull down the corresponding cs pin. any instruction can be issued to a slave device only while the cs pin is low. when the device is not selected, data through the si pin is ignored and the serial output pin (so) remains in a high-impedance state. note a new instruction must begin with the falling edge of cs . therefore, only one opcode can be issued for each active chip select cycle. serial clock (sck) the serial clock is generated by the spi master and the communication is synchronized with this clock after cs goes low. the cy15b004q enables spi modes 0 and 3 for data communication. in both of these modes, the inputs are latched by the slave device on the rising edge of sck and outputs are issued on the falling edge. therefor e, the first rising edge of sck signifies the arrival of the first bit (msb) of a spi instruction on the si pin. further, all data inputs and outputs are synchronized with sck. data transmission (si/so) the spi data bus consists of two lines, si and so, for serial data communication. si is also referred to as master out slave in (mosi) and so is referred to as master in slave out (miso). the
cy15b004q document number: 002-10032 rev. *c page 5 of 22 master issues instructions to t he slave through the si pin, while the slave responds through the so pin. multiple slave devices may share the si and so lines as described earlier. the cy15b004q has two separate pins for si and so, which can be connected with the master as shown in figure 2 . for a microcontroller that has no dedicated spi bus, a general-purpose port may be used. to reduce hardware resources on the controller, it is possible to connect the two data pins (si, so) together and tie off (high) the hold and wp pins. figure 3 shows such a configuration, which uses only three pins. most significant bit (msb) the spi protocol requires that the first bit to be transmitted is the most significant bit (msb). this is valid for both address and data transmission. the 4-kbit serial f-ram requires an opcode including the upper address bit, and a word address for any read or write operation. the word address consist of the lower 8-address bits. the complete address of 9 bits specifies each byte address uniquely. serial opcode after the slave device is selected with cs going low, the first byte received is treated as the opcode for the intended operation. cy15b004q uses the standard opcodes for memory accesses. invalid opcode if an invalid opcode is received, the opcode is ignored and the device ignores any additional serial data on the si pin until the next falling edge of cs , and the so pin remains tristated. status register cy15b004q has an 8-bit status register. the bits in the status register are used to configure the device. these bits are described in table 3 on page 7 . spi modes cy15b004q may be driven by a microcontroller with its spi peripheral running in either of the following two modes: spi mode 0 (cpol = 0, cpha = 0) spi mode 3 (cpol = 1, cpha = 1) figure 2. system configuration with spi port cs1 cs2 hold1 hold2 cy15b004q cy15b004q wp1 wp2 sck si so sck si so cs hold wp cs hold wp sck mosi miso spi microcontroller figure 3. system coniguration witout spi port cy15b004q microcontroller sck si so cs hold wp p1.2 p1.1 p1.0
cy15b004q document number: 002-10032 rev. *c page 6 of 22 for both these modes, the input data is latched in on the rising edge of sck starting from the first rising edge after cs goes active. if the clock starts from a high state (in mode 3), the first rising edge after the clock toggles is considered. the output data is available on the falling edge of sck. the two spi modes are shown in figure 4 and figure 5 . the status of the clock when the bus ma ster is not transferring data is: sck remains at 0 for mode 0 sck remains at 1 for mode 3 the device detects the spi mode fr om the status of the sck pin when the device is selected by bringing the cs pin low. if the sck pin is low when the device is selected, spi mode 0 is assumed and if the sck pin is high, it works in spi mode 3. power up to first access the cy15b004q is not accessible for a t pu time after power up. users must comply with the timing parameter t pu , which is the minimum time from v dd (min) to the first cs low. command structure there are six commands, called opcodes, that can be issued by the bus master to the cy15b004q. they are listed in table 1 . these opcodes control the functions performed by the memory. wren - set write enable latch the cy15b004q will power up wi th writes disabled. the wren command must be issued before any write operation. sending the wren opcode allows the user to issue subsequent opcodes for write operations. these incl ude writing the status register (wrsr) and writing the memory (write). sending the wren opcode causes the internal write enable latch to be set. a flag bit in the status register, called wel, indicates the state of t he latch. wel = ?1? indicates that writes are permitted. attempting to write the wel bit in the status register has no effect on the state of this bit ? only the wren opcode can set this bit. the wel bit will be aut omatically cleared on the rising edge of cs following a wrdi, a wrsr, or a write operation. this prevents further writes to t he status register or the f-ram array without another wren command. figure 6 illustrates the wren command bus configuration. note: the write enable latch (wel) bit in the status register of cy15b004q part doesn?t cl ear after executing the memory write (write) operation at memo ry location(s) from 0x100 to 0x1ff. for more information, see errata on page 19 . wrdi - reset write enable latch the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel is equal to ?0?. figure 7 illustrates the wrdi command bus configuration. figure 4. spi mode 0 figure 5. spi mode 3 table 1. opcode commands name description opcode wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr read status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 a011b write write memory data 0000 a010b lsb msb 76543210 cs sck si 01 2 3 4 5 67 cs sck si 765432 10 lsb msb 01 2 3 4 5 67 figure 6. wren bus configuration figure 7. wrdi bus configuration 0 0 0 0 0 1 1 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 0 cs sck si so hi-z 0 1 2 3 4 5 6 7 0 0 00 1
cy15b004q document number: 002-10032 rev. *c page 7 of 22 status register and write protection the write protection features of the cy15b004q are multi-tiered and are enabled through the status register. first, a wren opcode must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory are controlled by the wp pin and the status register. when wp is low, the entire part is write-protec ted. when wp is high, the memory protection is subject to t he status register. writes to the status register are perfo rmed using the wren and wrsr commands and subject to the wp pin. the status register is organized as follows. (the defaul t value shipped from the factory for bits in the status register is ?0?). bits 0 and 4?7 are fixed at ?0?; non e of these bits can be modified. note that bit 0 (?ready or write in progress? bit in serial flash and eeprom) is unnecessary, as the f-ram writes in real-time and is never busy, so it reads out as a ?0?. the bp1 and bp0 control the software write-protection f eatures and are nonvolatile bits. the wel flag indicates the state of the write enable latch. attempting to directly write the we l bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp1 and bp0 are memory block write protection bits. they specify portions of me mory that are write- protected as shown in ta b l e 4 . the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bits. the bp1 and bp0 bits allow software to selectively write protect the array. these settings are only used when the wp pin is inactive and the wren command has been issued. ta b l e 5 summarizes the write protection conditions. rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading the status register provides information about the current state of the write-protection features. fo llowing the rdsr opcode, the cy15b004q will return one byte with the contents of the status register. wrsr - write status register the wrsr command allows the spi bus master to write into the status register and change th e write protect configuration by setting the bp0 and bp1 bits as required. before issuing a wrsr command, the wp pin must be high or inactive. note that on the cy15b004q, wp prevents writing to the status register and the memory array. before sending the wrsr command, the user must send a wren command to enable writes. executing a wrsr command is a write operation and therefore, clears the write enable latch. table 2. status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x (0) x (0) x (0) x (0) bp1 (0) bp0 (0) wel (0) x (0) table 3. status register bit definition bit definition description bit 0 don?t care this bit is non-writable and always returns ?0? upon read. bit 1 (wel) write enable latch wel indicates if the device is write enabled. this bit defaults to ?0? (disabled) on power-up. wel = ?1? --> write enabled wel = ?0? --> write disabled bit 2 (bp0) block protect bit ?0? used for block protection. for details, see ta b l e 4 . bit 3 (bp1) block protect bit ?1? used for block protection. for details, see ta b l e 4 . bit 4-7 don?t care these bits are non-writable and always return ?0? upon read. table 4. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 180h to 1ffh (upper 1/4) 1 0 100h to 1ffh (upper 1/2) 1 1 000h to 1ffh (all) table 5. write protection wel wp protected blocks unprotected blocks status register 0 x protected protected protected 1 0 protected protected protected 1 1 protected unprotected unprotected
cy15b004q document number: 002-10032 rev. *c page 8 of 22 memory operation the spi interface, which is capable of a high clock frequency, highlights the fast write capability of the f-ram technology. unlike serial flash and eeproms, the cy15b004q can perform sequential writes at bus speed. no page register is needed and any number of sequential wr ites may be performed. write operation all writes to the memory begin with a wren opcode. the write opcode includes the upper bit of the memory address. bit 3 in the opcode corresponds to the upper address bit (a8). the next byte is the lower 8-bits of the address (a7?a0). in total, the 9-bits specify the address of the first byte of the write operation. subsequent bytes are data bytes, which are written sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and keeps cs low. if the last address of 1ffh is reached, the counter will roll over to 000h. data is written msb first. the rising edge of cs terminates a write operation. a write operation is shown in figure 10 on page 9 . note when a burst write reaches a protected block address, the automatic address increment stops and all the subsequent data bytes received for write will be ignored by the device. eeproms use page buffers to in crease their write throughput. this compensates for the technology?s inherently slow write operations. f-ram memories do not have page buffers because each byte is written to the f-ram array immediately after it is clocked in (after the eighth clock). this allows any number of bytes to be written without page buffer delays. note if the power is lost in the mi ddle of the write operation, only the last completed byte will be written. read operation after the falling edge of cs , the bus master can issue a read opcode. the read opcode includes the upper bit of the memory address. bit 3 in the opcode corresponds to the upper address bit (a8). the next byte is the lower 8-bits of the address (a7?a0). in total, the 9-bits specify the address of the first byte of the read operation. after the opcode and address are issued, the device drives out the read data on the ne xt eight clocks. the si input is ignored during read data bytes. subsequent bytes are data bytes, which are read out sequentially. addresses are incremented internally as long as the bus master continues to issue clocks and cs is low. if the la st address of 1ffh is reached, the counter will roll over to 000h. data is read msb first. the rising edge of cs terminates a read operation and tristates the so pin. a read operation is shown in figure 11 on page 9 . figure 8. rdsr bus configuration figure 9. wrsr bus configuration (wren not shown) cs sck so 01234567 si 000001 0 0 1 hi-z 012345 67 lsb d0 d1 d2 d3 d4 d5 d6 msb d7 opcode data cs sck so 0123 4567 si 00000001 msb lsb d2 d3 x hi-z 01234 567 opcode data x x x x x
cy15b004q document number: 002-10032 rev. *c page 9 of 22 hold pin operation the hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the hold pin low while sck is low, the current operati on will pause. taking the hold pin high while sck is low will resume an operation. the transitions of hold must occur while sck is low, but the sck and cs can toggle during a hold state. figure 10. memory write (wren not shown) figure 11. memory read cs sck so 01234 5 6 70 7 6 5 4 3 2 1 01234567 msb lsb data d0 d1 d2 d3 d4 d5 d6 d7 si opcode 0000 a8 01 a7 a6 a5 a4 a3 a1 0 a2 a0 byte address msb lsb hi-z cs sck so 01 23456 70 7 6 5 4 3 2 1 012345 6 7 msb lsb data si opcode 0000 a8 01 a7 a6 a5 a4 a3 a1 1 a2 a0 byte address msb lsb d0 d1 d2 d3 d4 d5 d6 d7 hi-z figure 12. hold operation [2] cs sck hold so ~ ~ ~ ~ si valid in valid in note 2. figure shows hold operation for input mode and output mode.
cy15b004q document number: 002-10032 rev. *c page 10 of 22 endurance the cy15b004q devices are capabl e of being accessed at least 10 13 times, reads or writes. an f-ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f-ram architec ture is based on an array of rows and columns of 64 rows of 64-bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. ta b l e 6 shows endurance calculations for a 64-byte repeating loop, which includes an opcode, a starting address, and a sequential 64-byte data stream. this causes each byte to experience one endurance cycle through the loop. table 6. time to reach endurance limit for repeating 64-byte loop sck freq (mhz) endurance cycles/sec endurance cycles/year years to reach limit 10 18,660 5.88 10 11 17.0 5 9,330 2.94 10 11 34.0 1 1,870 5.88 10 10 170.1
cy15b004q document number: 002-10032 rev. *c page 11 of 22 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?55 c to +150 c maximum accumulated storage time at 150 c ambient temperature ................................. 1000 h at 125 c ambient temperature ................................11000 h at 85 c ambient temperature .............................. 121 years ambient temperature with power applied ..... ............... ............... ?55 c to +125 c supply voltage on v dd relative to v ss .........?1.0 v to +5.0 v input voltage ............. ?1.0 v to +5.0 v and v in < v dd +1.0 v dc voltage applied to outputs in high z state .................................... ?0.5 v to v dd + 0.5 v transient voltage (< 20 ns) on any pin to ground potential ............ ?2.0 v to v dd + 2.0 v package power dissipation capability (t a = 25 c) ............................... 1.0 w surface mount lead soldering temperature (3 seconds) .......................... +260 c dc output current (1 output at a time, 1s duration) .... 15 ma electrostatic discharge voltage [3] human body model (aec-q100-002 rev. e) ................... 2 kv charged device model (aec-q100-011 rev. b) .............. 500 v latch up current ..................................................... > 140 ma operating range range ambient temperature (t a ) v dd automotive-e ?40 c to +125 c 3.0 v to 3.6 v dc electrical characteristics over the operating range parameter description test conditions min typ [4] max unit v dd power supply 3.0 3.3 3.6 v i dd v dd supply current sck toggling between v dd ? 0.3 v and v ss , other inputs v ss or v dd ? 0.3 v. so = open. f sck = 1 mhz ? ? 0.2 ma f sck = 10 mhz ? ? 2 ma f sck = 16 mhz ? ? 3.0 ma i sb v dd standby current cs = v dd . all other inputs v ss or v dd . t a = 85 c??6 a t a = 125 c ? ? 20 a i li input leakage current v ss < v in < v dd ??1 a i lo output leakage current v ss < v out < v dd ??1 a v ih input high voltage 0.75 v dd ?v dd + 0.3 v v il input low voltage ? 0.3 ? 0.25 v dd v v oh output high voltage i oh = ?2 ma v dd ? 0.8 ? ? v v ol output low voltage i ol = 2 ma ? ? 0.4 v v hys [5] input hysteresis (cs and sck pin) 0.05 v dd ??v notes 3. electrostatic discharge voltages specifi ed in the datasheet are the aec-q100 standard limits used for qualifying the device. to know the maximum value device passes for, please refer to the device qualification report available on the website. 4. typical values are at 25 c, v dd = v dd (typ). not 100% tested. 5. this parameter is characterized but not 100% tested.
cy15b004q document number: 002-10032 rev. *c page 12 of 22 ac test conditions input pulse levels .................................10% and 90% of v dd input rise and fall times ...................................................5 ns input and output timing reference levels ................0.5 v dd output load capacitance .............................................. 30 pf data retention and endurance parameter description test condition min max unit t dr data retention t a = 125 c 11000 ? hours t a = 105 c11?years t a = 85 c 121 ? nv c endurance over operating temperature 10 13 ? cycles example of an f-ra m life time in an aec-q100 automotive application an application does not operate under a steady temperature for t he entire usage life time of the application. instead, it is of ten expected to operate in multiple temperature environments throughout the application?s usage life time. accordingly, the retention specif ication for f-ram in applications often needs to be calculated cumulative ly. an example calculation for a multi-temperature thermal pro files is given below. tempeature t time factor t acceleration factor with respect to tmax a [6] profile factor p profile life time l (p) t1 = 125 c t1 = 0.1 a1 = 1 8.33 > 10.46 years t2 = 105 c t2 = 0.15 a2 = 8.67 t3 = 85 c t3 = 0.25 a3 = 95.68 t4 = 55 c t4 = 0.50 a4 = 6074.80 a lt () ltmax () ------------------------ e ea k ------- 1 t --- 1 tmax --------------- - ? ?? ?? == p 1 t1 a1 ------- t2 a2 ------- t3 a3 ------- t4 a4 ------- +++ ?? ?? ------------------------------------------------------- - = lp () pltmax () = capacitance parameter [7] description test conditions max unit c o output pin capacitance (so) t a = 25 c, f = 1 mhz, v dd = v dd (typ) 8 pf c i input pin capacitance 6pf thermal resistance parameter [7] description test conditions 8-pin soic unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 148 c/w jc thermal resistance (junction to case) 48 c/w notes 6. where k is the boltzmann constant 8.617 10 -5 ev/k, tmax is the highest temperature specified for the product, and t is an y temperature within the f-ram product specification. all temperatures are in kelvin in the equation. 7. this parameter is characterized but not 100% tested.
cy15b004q document number: 002-10032 rev. *c page 13 of 22 ac switching characteristics over the operating range parameters [8] description min max min max unit cypress parameter alt. parameter f sck ? sck clock frequency 0 10 0 16 mhz t ch ? clock high time 40 ? 25 ? ns t cl ? clock low time 40 ? 25 ? ns t csu t css chip select setup 10 ? 10 ? ns t csh t csh chip select hold 10 ? 10 ? ns t od [9, 10] t hzcs output disable time ? 30 ? 20 ns t odv t co output data valid time ? 35 ? 25 ns t oh ? output hold time 0 ? 0 ? ns t d ? deselect time 100 ? 60 ? ns t r [11, 12] ? data in rise time ? 50 ? 50 ns t f [11, 12] ? data in fall time ? 50 ? 50 ns t su t sd data setup time 5 ? 5 ? ns t h t hd data hold time 5 ? 5 ? ns t hs t sh hold setup time 10 ? 10 ? ns t hh t hh hold hold time 10 ? 10 ? ns t hz [9, 10] t hhz hold low to hi-z ? 30 ? 20 ns t lz [10] t hlz hold high to data active ? 30 ? 20 ns notes 8. test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 v dd , input pulse levels of 10% to 90% of v dd , and output loading of the specified i ol /i oh and 30 pf load capacitance shown in ac test conditions on page 12 . 9. t od and t hz are specified with a load capacitance of 5 pf. transiti on is measured when the outputs enter a high impedance state. 10. this parameter is characterized but not 100% tested. 11. rise and fall times measured between 10% and 90% of waveform. 12. these parameters are guaranteed by design and are not tested.
cy15b004q document number: 002-10032 rev. *c page 14 of 22 figure 13. synchronous data timing (mode 0) figure 14. hold timing hi-z valid in hi-z cs sck si so t cl t ch t csu t su t h t odv t oh t d t csh t od valid in valid in cs sck hold so t hs t hz t lz t hh t hs t hh ~ ~ ~ ~ si t su valid in valid in
cy15b004q document number: 002-10032 rev. *c page 15 of 22 power cycle timing over the operating range parameter description min max unit t pu power-up v dd (min) to first access (cs low) 1 ? ms t pd last access (cs high) to power-down (v dd (min)) 0 ? s t vr [13] v dd power-up ramp rate 30 ? s/v t vf [13] v dd power-down ramp rate 20 ? s/v figure 15. power cycle timing cs ~ ~ ~ ~ t pu t vr t vf v dd v dd(min) t pd v dd(min) note 13. slope measured at any point on v dd waveform.
cy15b004q document number: 002-10032 rev. *c page 16 of 22 ordering code definitions ordering information ordering code package diagram package type operating range CY15B004Q-SXE 51-85066 8-pin soic automotive-e all these parts are pb-free. contact your local cypre ss sales representative for availability of these parts. option: x = blank or t blank = standard; t = tape and reel temperature range: e = automotive-e (?40 c to +125 c) x = pb-free package type: s = 8-pin soic q = spi f-ram density: 004 = 4-kbit voltage: b = 3.0 v to 3.6 v f-ram company id: cy = cypress 15 cy b 004 q s x e x -
cy15b004q document number: 002-10032 rev. *c page 17 of 22 package diagrams figure 16. 8-pin soic (150 mils) package outline, 51-85066 51-85066 *h
cy15b004q document number: 002-10032 rev. *c page 18 of 22 acronyms document conventions units of measure acronym description aec automotive electronics council cpha clock phase cpol clock polarity eeprom electrically erasable programmable read-only memory eia electronic industries alliance i/o input/output jedec joint electron devices engineering council jesd jedec standards lsb least significant bit msb most significant bit f-ram ferroelectric random access memory rohs restriction of hazardous substances spi serial peripheral interface soic small outline integrated circuit symbol unit of measure c degrees celsius hz hertz khz kilohertz k kilohms kbit kilobits kv kilovolts mhz megahertz a microamperes s microseconds ma milliamperes ms milliseconds ns nanoseconds ohms % percent pf picofarads v volts w watts
cy15b004q document number: 002-10032 rev. *c page 19 of 22 errata this section describes the errata for the 4kb spi f-ram (512 8, spi) products. details include errata trigger conditions, sco pe of impact, available workarounds, and silicon revision applicability. compare this document with th e device datasheet for complete functional differences. contact your local cypress sales represent ative if you have questions. you can also send your related queries directly to fram@cypress.com . part numbers affected qualification status production parts. errata summary the following table defines the errata applicability. 1. the write enable latch (wel) bit in the status register of cy 15b004q part doesn?t clear after executing the memory write (wri te) operation at memory location(s) from 0x100 to 0x1ff. problem definition as per the cy15b004q datasheet ?sending the wren opcode causes the internal write enable latch (wel) to be set. a flag bit in the status register, called wel, indicate s the state of the latch. wel = 1 indicate s that writes are permitted. attempting t o write the wel bit in the status register has no effect. completing any write operation will automatica lly clear the write-enable latc h and will prevent further writes wi thout another wren command?. however, in the cy15b004q part, the wel bit doesn?t clear auto matically after writing at any memory location(s) from 0x100 to 0x1ff. that means, after completi ng the write cycle with the opcode byte 0x0a, we l bit in status regist er is still set and henc e a further write can be issued wit hout sending the wren opcode. part number device characteristics cy15b004q 512 8, 3.0 v to 3.6 v, single power supply, se rial (spi) interface f-ram in 8-pin soic package. items part number silicon revision fix status the write enable latch (wel) bit in the status register of cy15b004q part doesn?t clear after executing the memory write (write) operation at memory location(s) from 0x100 to 0x1ff. CY15B004Q-SXE rev *a none. this behavior is applicable to all listed parts in the production.
cy15b004q document number: 002-10032 rev. *c page 20 of 22 status register status register bit definition the internal state machine of cy15b004q is intended to clea r the wel bit after executing write opcodes (write and wrsr). however, as explained above, the wel doesn?t clear when executing the memory write (w rite) at location/s from 0x100 to 0x1ff. the 4kb memory requires 9 address bits to map the entire memory array (512 8). to optimize the command cycle and to maintain the compatibility with the i ndustry standard 4kb spi eeprom s, the msb of the address (9 th bit) in the 4kb device is embedded into write (write) and read (read) opcodes as shown below. for address range ? 0x00 to 0xff: write opcode ? 0000 a 010 = 0x0000 0 010 (or 0x02 in hex, a = ?0?) read opcode ? 0000 a 011 = 0x0000 0 011 (or 0x03 in hex, a = ?0?) for address range ? 0x100 to 0x1ff: write opcode ? 0000 a 010 = 0x0000 1 010 (or 0x0a in hex, a = ?1?) read opcode ? 0000 a 011 = 0x0000 1 011 (or 0x0b in hex, a = ?1?) due to a logic bug in the cy15b004q state machine, the opcode byte 0x0a does not trigger clearing of wel bit, hence the wel bit remains set even after executing the memory wr ite at address location/s from 0x100 to 0x1ff. parameters affected none. trigger condition(s) execute the write enable command (wren) followed by the writ e command (write) to memory address range 0x100 to 0x1ff. scope of impact none. it only allows a subsequent write (write or wrsr) without sending a prior wren command. workaround to ensure that the wel bit is cleared after every write, the spi host controller can issue the wr ite disable (wrdi) opcode at t he end of every write cycle (after cs goes high). the wrdi command clears the wel (if set) and disables all writes until the wel is set by sending the wren opcode before initiating a new write operation. fix status there is no fix planned and all the cy15b004q pa rt in production will continue with the above errata.
cy15b004q document number: 002-10032 rev. *c page 21 of 22 document history page document title: cy15b004q, 4-kbit (512 8) serial (spi) automotive f-ram document number: 002-10032 rev. ecn no. orig. of change submission date description of change ** 5032342 gvch 12/15/2015 new data sheet. *a 5124930 gvch 02/04/2016 updated dc electrical characteristics : changed maximum value of i dd parameter corresponding to test condition ?f sck = 16 mhz? from 3.2 ma to 3.0 ma. *b 5573964 gvch 01/23/2017 changed status from summary to final. updated serial peripheral interface ? spi bus : updated wren - set write enable latch : updated description (added note regarding errata). updated maximum ratings : updated electrostatic discharge voltage: changed value of ?human body model? from 4 kv to 2 kv. changed value of ?charged device model? from 1.25 kv to 500 v. removed ?machine model? related information. updated ordering information : updated part numbers. added errata . updated to new template. *c 5685431 gvch 04/05/2017 updated maximum ratings : added note 3 and referred the same note in ?electrostatic discharge voltage?. updated to new template.
document number: 002-10032 rev. *c revised april 5, 2017 page 22 of 22 cy15b004q ? cypress semiconductor corporation, 2015?2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage ("unintended uses"). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all uninte nded uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/pmic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support

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